Technical Field
This disclosure relates to computer processors, and more particularly to techniques for completing load and store instructions in a weakly-ordered memory model.
Description of the Related Art
Modern out-of-order processors are often configured to execute load and store instructions out-of-order, and also permit loads to access memory in a speculative manner. Speculatively-executed loads and stores are typically held in queues until necessary criteria is met to make the loads and stores architecturally visible (i.e., visible to software). The order rules of memory accesses by various processors is defined by the memory consistency model specified by a given instruction set architecture (ISA). The weakly-ordered model is one such memory consistency model.
One relaxed rule of the weakly-ordered model is that younger loads are permitted to access memory and complete ahead of relatively older stores as long as memory-address based dependencies are adhered to.